1. Field of the Invention
This invention relates to the field of semiconductor circuit manufacturing, and more specifically, to a method of precleaning an intermetal dielectric layer to promote photoresist adhesion during a via hole formation.
2. Prior Art
Large scale integrated semiconductor circuits have multiple layers of conducting films interconnecting the various devices located on a semiconductor substrate. Modern integrated circuits known as multilevel integrated circuits typically have at least two metal layers and the most advanced have three or more: the first level of metalization (metal 1) provides for local interconnects while the later metalization layers (metal 2 or metal 3, etc.) provide for longer interconnects, (i.e., across the entire chip). The conducting layers are normally separated by an intermetal dielectric layer consisting of an oxide, such as SiO.sub.2, which acts to isolate the electric potential of the individual conducting layers.
When it is desired to electrically couple conducting lines of different metal layers, a multilevel interconnect is formed. When this is the case, a hole is etched through the intermetal dielectric layer at the location the interconnect is desired. When the upper metal layer (metal 2 or 3 or 4) is subsequently deposited, it is able to form a contact with the lower level metal (metal 1 or 2 or 3) at the desired location. Such holes formed in intermetal dielectric layers are commonly referred to in the art as "via holes". Processes for etching via holes are well known in the art.
Most processes for etching via holes can be broken into three distinct groups: wet etching processes, dry etching processes, and wet/dry etching processes. Each technique has its inherent benefits and short comings. The choice of which process to use is typically dictated by the following considerations: the size of the vias to be formed, the packing density of the vias, the cost of manufacturing the vias, and the desired reliability of the vias.
Wet etching found widespread acceptance in early semiconductor manufacturing. Wet etching of vias into an intermetal dielectric such as SiO.sub.2 is typically accomplished using various HF solutions. (HF readily attacks SiO.sub.2 at room temperature.) A problem with wet etching is that its processes are generally isotropic in nature. That is, there is as much etching in the horizontal plane as there is in the vertical plane. An advantage of the isotropic nature of wet etching is that the formed metal contacts are very reliable since the vias have a "tapered" or rounded profile and therefore allow for excellent metal step coverage. A disadvantage of the isotropic nature of wet etching, however, is mask undercutting. The undercutting makes wet etching inappropriate for defining features spaced less than 3 microns wide. Another problem with wet etching is that the photoresist or masking material used to define the via location must adhere well during chemical etching to ensure proper patterning. Wet etching processes are inadequate for making small dimensioned vias necessary for modern high device density integrated circuits.
Dry etching is another well known method of etching via interconnections into intermetal dielectric layers. Dry etching techniques include physical sputter etching, reactive ion etching, and plasma etching. Dry etching techniques yield a much more anisotropic (non-isotropic) etch than do wet etching techniques. That is, dry etching forms contact holes with nearly vertical side walls. Dry etching techniques are very useful for generating high density vias because they result in very little undercutting of the resist mask (i.e., they reproduce the features on the resist mask with fidelity). Since dry etching creates vias with nearly vertical sidewalls, poor metal step coverage may result and unreliable contacts may be formed. To ensure reliable metal contacts, therefore, tungsten plugs are necessary to fill the vias. Such processes are extremely expensive and process intensive.
In order to generate modern size multilevel interconnects or vias in a cost effective and reliable manner, a third technique known as wet/dry etching has been developed. In wet/dry etching techniques a wet etch is used first to isotropically etch the top portion of the via, and then a dry etch is used to anisotropically etch the remainder of the via. This technique encompasses the benefits of both wet and dry etching by forming a via with tapered sidewalls at the top and vertical sidewalls at the bottom. The tapered sidewalls at the top ensure good metal step coverage necessary for reliable contacts. Thus, the need for expensive and process intensive tungsten plugs is eliminated. Additionally, the vertical sidewalls at the bottom of the via allow the manufacturing of vias with dimensions of less than one micron. Hence, wet/dry etched vias can be closely packed, which is a necessity for modern high device density integrated circuits.
Another important consideration in the fabrication of modern multi-level interconnect semiconductor circuits is the intermetal dielectric and its method of fabrication. First, the dielectric layer must be able to electrically and physically isolate one level of a conductor (metal 1) from another in a multi-level interconnect system. A good intermetal dielectric layer, therefore, should exhibit good physical and electrical characteristics such as dielectric constant, adhesion to metal, and moisture absorption. Secondly, a good dielectric must also be able to be formed pin hole free and at low temperatures in order to be compatible with low melting point metals, such as aluminum, which will already be present on the wafer when the intermetal dielectric layer is formed.
The intermetal dielectric layer must also be able to be formed between spaces less than one micron without void formation due to cusping. This is because in modern integrated circuits, the spacing between metal lines of a particular metalization level has decreased in order to increase device density. Modern circuits have metal lines spaced less than one micron. These close steps are susceptible to creating voids in the dielectric when the dielectric is formed. Void formation adversely affects device reliability.
Also essential in the manufacturing of multi-level interconnect devices is the planarization of the resultant intermetal dielectric layer. Planarization is necessary because as the number of levels in interconnect technology is increased, the stacking of the additional layers on top of one another produces a more and more rugged topography. This is especially a problem for technologies which employ two levels of polysilicon such as the manufacturing of EPROMs or EPLDs. Poor topography in such devices can result in poor metal step coverage of metal lines, metal stingers, and poor optical lithography. A planar dielectric surface, therefore, is essential for the fabrication of reliable electrical connections in multi-level interconnect systems.
One of the few present dielectrics which exhibit good physical and electrical characteristics, as well as planar topographies without void formation in the smallest cross sectional areas, are "dep-etch" intermetal dielectrics. Such dielectrics are well known in the art. For instance, an article published in the 1989 proceedings of the Sixth International IEEE VLSI Multi-Level Interconnection Conference entitled "A Single Pass, In-situ Planarization Process Utilizing TEOS for Double-Poly, Double-Metal CMOS Technologies" by Sunil Mehta and Gian Sharma, describes such a dielectric. This technique employs two plasma depositions of TEOS (tetraethyl orthosilicate), a plasma TEOS oxide (PECVD) and a thermal TEOS oxide (THCVD). First, the PECVD oxide is deposited, then an argon sputter etch is used to taper the oxide profile. Next, a second deposition, a thermal oxide deposition, is made which exhibits excellent conformality. This deposition, like the previous deposition, is followed by a dry etch to achieve the desired dielectric thickness. Hence, the process gives rise to the name "dep-etch". An alternative dep-etch process is detailed in "In-situ Planarization of Dielectric Surfaces Using Boron Oxide" by Jeffrey Marks, Cam Lau and David Wang, of Applied Materials of Santa Clara, Calif., published in the 1989 VMIC Conference of IEEE, Jun. 12-13. Dep-etch intermetal dielectrics are essential in the fabrication of modern high density multi-level integrated circuits.
Although the "dep etch" technique produces an ideal intermetal dielectric layer for multi-level interconnect integrated circuits, it has an unfortunate and very serious side effect. During the dry etching portion of the dep-etch process, a thin polymer film forms on top of the dielectric layer. The thin film causes poor adhesion between the TEOS(dielectric layer) and a later formed photoresist masking layer used to define the via location. It is essential in the development of modern semiconductor circuits that the photoresist exhibit good adhesion to the intermetal dielectric layer. Poor adhesion can cause sever undercutting, loss of resolution, and possibly even complete loss of pattern.
As discussed above, the most cost effective method of producing reliable, small vias is to use a wet/dry chemical etching process. Resist adhesion, unfortunately, is most important for techniques which employ a wet or chemical etching such as the wet/dry etch. Therefore, in order to make the dep-etch intermetal dielectric formation process compatible with the wet/dry via etch process, photoresist adhesion to the dielectric layer must be improved.
Additionally, even if the more expensive method of dry etching vias and filling them with tungsten plugs is employed, the polymer film can still create problems. Although not as dependent upon resist adhesion as chemical etching techniques, dry etching still requires good resist adhesion to withstand the developing step of the photolithography process. This problem is compounded as via feature sizes shrink to meet the demands of high density integrated circuits.
Various techniques are well known in the art which help promote resist adhesion. For instance, dehydration brakes prior to resist coating, use of resist adhesion promoter such as HMDS, and elevated temperature post bake cycles are all well-known methods to increase resist adhesion. None of these techniques, however, is useful in removing the polymer film formed on the TEOS intermetal dielectric during the dep-etch process and, therefore, none is completely successful in promoting resist adhesion in the present case.
Additionally, presently known wafer cleaning procedures have likewise proved ineffective in removing the polymer film. Conventional chemical cleaning methods are typically performed with a series of acid baths. Acids such as HF and HCl are incompatible with the TEOS intermetal dielectric layer. Since the intermetal dielectric layer is an oxide, the dielectric would readily react with these acids and the integrity of the dielectric would be affected. Additionally, acids such as H.sub.2 SO.sub.4 are incompatible with metals already present on the water. A cleaning solution is required which will remove the polymer film without significantly etching the TEOS oxide intermetal dielectric layer or affecting materials already present on the wafer.
Thus, what is needed to fabricate less expensive, modern, reliable, high density, multi-level integrated semiconductor circuits is a method to preclean the TEOS oxide and thereby remove the polymer film inadvertently formed during the TEOS dep etch process. Once the polymer film has been removed, good adhesion will result which will allow the use of a wet/dry etching technique for via formation.